Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency


Department of ECE, National Institute of Technology, Agartala. Agartala, India


Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can minimize the number of switching activity between two successive patterns. The switching power dissipation of the Circuit under Test (CUT) also depends on the order of patterns applied for. If consecutive pattern application time is sufficiently large then leakage power dissipation does not alter on the ordering of the patterns. So under this circumstances leakage power does not change but if the pattern application time is small leakage power depends on the ordering of the pattern applied to the CUT. Previous works concerns only about don’t care filling or pattern ordering or first filling of don’t care and then ordering for low power circuit testing. Ordering after filling of don’t care may change the benefits of X-filling. The advantage of test power reduction of both the methods - don’t care filling and ordering may be obtained if they are considered together. In this work an approach based on Genetic Algorithm (GA) is used to solve the integrated problem for X-filling and reordering of test patterns considering pattern dependency to minimize the switching activity throughout testing without changing the fault coverage. Effectiveness of the proposed GA based approach compared to existing approach considering test patterns for ISCAS’85 benchmark circuits is shown in the result section.


1.     Wang, S., "A bist tpg for low power dissipation and high fault coverage", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 15, No. 7, (2007), 777-789.
2.     Wilson, L., "International technology roadmap for semiconductors (ITRS)", Semiconductor Industry Association,  (2005).
3.     Bushnell, M. and Agrawal, V., "Essentials of electronic testing for
digital, memory and mixed-signal vlsi circuits, Springer Science & Business Media,  Vol. 17,  (2000).
4.     Shi, C. and Kapur, R., "How power-aware test improves reliability and yield", IEEDesign. com, September,  Vol. 15, No., (2004).
5.     Lin, Y.-S. and Sylvester, D., "Runtime leakage power estimation technique for combinational circuits", in Proceedings of the 2007 Asia and South Pacific Design Automation Conference, IEEE Computer Society., (2007), 660-665.
6.     Kumar, S.K., Kaundinya, S., Kundu, S. and Chattopadhyay, S., "Particle swarm optimization based vector reordering for low power testing", in Computing Communication and Networking Technologies (ICCCNT), 2010 International Conference on, IEEE., (2010), 1-5.
7.     Badereddine, N., Girard, P., Pravossoudovitch, S., Landrault, C., Virazel, A. and Wunderlich, H.-J., "Minimizing peak power consumption during scan testing: Test pattern modification with x filling heuristics", in Design and Test of Integrated Systems in Nanoscale Technology. DTIS 2006. International Conference on, IEEE., (2006), 359-364.
8.     Kumar, S.K., Kaundinya, S., Kundu, S. and Chattopadhyay, S., "Customizing pattern set for test power reduction via improved x-identification and reordering", in Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, ACM., (2010), 177-182.
9.     Chattopadhyay, S. and Choudhary, N., "Genetic algorithm based approach for low power combinational circuit testing", in VLSI Design, 2003. Proceedings. 16th International Conference on, DOI: 10.1109/ICVD.2003.1183192, IEEE., (2003), 552-557.
10.   Seomun, J., Shin, I. and Shin, Y., "Synthesis of active-mode power-gating circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,  Vol. 31, No. 3, (2012), 391-403.
11.   Choudhury, P. and Pradhan, S.N., "An approach for low power design of power gated finite state machines considering partitioning and state encoding together", Journal of Low Power Electronics,  Vol. 8, No. 4, (2012), 452-463.