ECE, National Institute of Technology, Agartala
ECE, National Institute of technology, Agartala
In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the analog circuit, is designed and is taken for testing purpose. Fault coverage is identified after fault modeling, fault injection and fault simulation. More than 93% fault coverage is achieved and there is a scope of increasing more fault coverage. Since analog testing prefaces the challenge of power dissipation during testing, some power minimization techniques like sleepy stack method and current correlation method have adhered during the testing process. Test power reduction up to 84 % is achieved in this work.