Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

Document Type : Original Article

Authors

Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh, India

Abstract

Two-dimensional analytical modelling of Dual Material Gate Tunnel Field Effect Transistor with change in variation of gate oxide thickness (DMG-UOX-TFET) is proposed in this work. This proposed device employs dielectric materials such as hafnium oxide and silicon dioxide, with distinct oxide thicknesses. This device was invented using a technology-aided computer design tool in 10 nm (0.01 µm) technology. This work investigates the impact of gate oxide thickness on the electrical characteristics of the proposed device, with a particular focus on drain current variation. The extensive simulations and key performance parameters of the proposed device were analyzed regarding gate oxide thickness. The various gate oxide thicknesses and their effects on the device subthreshold slope, On- current, Off- current, and on-off-current ratio were analyzed. The proposed device incorporates n-type operations within the gate overlap region, effectively mitigating the corner effect and the detrimental band-to-band tunneling that can degrade the on/off ratio. Through careful optimization of the doping concentration in the gate overlap region, achieved a remarkable ∼4.8 time enhancement in the on-current, while simultaneously reducing the average subthreshold swing from 91.3 mV/dec to 52.8 mV/dec.

Graphical Abstract

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

Keywords

Main Subjects

References

  1. Howldar S, Balaji B, Srinivasa Rao K. Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2023;36(12):2137-44. 10.5829/ije.2023.36.12c.01
  2. Venkatesh M, Suguna M, Balamurugan N. Influence of germanium source dual halo dual dielectric triple material surrounding gate tunnel FET for improved analog/RF performance. Silicon. 2020;12:2869-77. http://link.springer.com/article/10.1007/s12633-020-00385-6
  3. Raju V, Sivasankaran K. Performance analysis of double gate Junctionless tunnel field effect transistor: RF stability perspective. International Journal of Advanced Computer Science and Applications. 2019;10(11). https://doi.org/10.1456/IJACSA.2019.010117
  4. Madan J, Pandey R, Sharma R, Chaujar R. Impact of metal silicide source electrode on polarity gate induced source in junctionless TFET. Applied Physics A. 2019;125(9):600. https://doi.org/10.1007/s00339-019-2900-6
  5. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ. A line tunneling field-effect transistor based on misaligned core–shell gate architecture in emerging nanotube FETs. IEEE Transactions on Electron Devices. 2019;66(6):2809-16. https://doi.org/10.1109/TED.2019.2910156
  6. Zare M, Peyravi F, Hosseini SE. Impact of hetero-dielectric ferroelectric gate stack on analog/RF performance of tunnel FET. Journal of Electronic Materials. 2020;49:5638-46. https://doi.org/10.1007/s11664-020-08315-3
  7. Meshkin R. An Extended-Source Tunneling-FET with Gate-Overlapped n+-Doped Pocket. Journal of Electronic Materials. 2023:1-7. https://doi.org/10.1007/s11664-023-10524-5
  8. Radhamma E, Vemana Chary D, Krishnamurthy A, Venkatarami Reddy D, Sreenivasa Rao D, Gowthami Y, et al. Performance analysis of high-k dielectric heterojunction high electron mobility transistor for rf applications. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1652-8. 10.5829/ije.2023.36.09c.09
  9. Gowthami Y, Balaji B, Srinivasa Rao K. Performance Analysis and Optimization of Asymmetric Front and Back Pi Gates with Dual Material in Gallium Nitride High Electron Mobility Transistor for Nano Electronics Application. International Journal of Engineering, Transactions A: Basics 2023;36(7):1269-77. 10.5829/ije.2023.36.07a.08
  10. Keighobadi D, Mohammadi S, Mohtaram M. Recessed gate cylindrical heterostructure TFET, a device with extremely steep subthreshold swing. Transactions on Electrical and Electronic Materials. 2021:1-7. https://doi.org/10.1007/s42341-021-00321-4
  11. Wangkheirakpam VD, Bhowmick B, Pukhrambam PD. Investigation of a dual MOSCAP TFET with improved vertical tunneling and its near-infrared sensing application. Semiconductor Science and Technology. 2020;35(6):065013. https://doi.org/10.1088/1361-6641/ab8172
  12. Gowthami Y, Balaji B, Rao KS. Design and performance evaluation of 6nm hemt with silicon sapphire substrate. Silicon. 2022;14(17):11797-804. https://doi.org/10.1007/s12633-022-01900-7
  13. Kumar PK, Balaji B, Rao KS. Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering. Silicon. 2022;14(16):10423-36. https://doi.org/10.1007/s12633-022-01747-y
  14. Howldar S, Balaji B, Srinivasa Rao K. Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device. International Journal of Engineering, Transactions C: Aspects 2023;36(6):1129-35. 10.5829/ije.2023.36.06c.11
  15. Anvarifard MK, Orouji AA. Enhancement of a nanoscale novel Esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations. Silicon. 2019;11(6):2547-56. https://doi.org/10.1007/s12633-018-0043-6
  16. Dixit A, Gupta N. A compact model of gate capacitance in ballistic gate-all-around carbon nanotube field effect transistors. International Journal of Engineering, Transactions A: Basics. 2021;34(7):1718-24. 10.5829/IJE.2021.34.07A.16
  17. Raj A, Singh S, Priyadarshani KN, Arya R, Naugarhiya A. Vertically Extended Drain Double Gate S i 1− x G ex Source Tunnel FET: Proposal & Investigation For Optimized Device Performance. Silicon. 2021;13:2589-604. https://doi.org/10.1007/s12633-02000603-1
  18. Chakrabarty R, Roy S, Pathak T, Kumar Mandal N. Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization. International Journal of Engineering, Transactions C: Aspects. 2021;34(12):2672-8. 10.5829/ije.2021.34.12c.13
  19. Gopal G, Varma T. Simulation-based analysis of ultra thin-body double gate ferroelectric TFET for an enhanced electric performance. Silicon. 2022;14(12):6553-63. https://doi.org/10.1007/s12633-021-01428-2
  20. Roy A, Mitra R, Kundu A, editors. Influence of channel thickness on analog and RF performance enhancement of an underlap DG AlGaN/GaN based MOS-HEMT device. 2019 Devices for Integrated Circuit (DevIC); 2019: IEEE.
  21. Gedam A, Acharya B, Mishra GP. Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon. 2021;13:167-78. https://doi.org/10.1007/s12633-020-00410-8
  22. Mehrabani AH, Fattah A, Rahimi E. Design and Simulation of a Novel Hetero-junction Bipolar Transistor with Gate-Controlled Current Gain. International Journal of Engineering, Transactions C: Aspects 2023;36(03):433. 10.5829/ije.2023.36.03c.01
  23. Rafiee A, Nickabadi S, Nobarian M, Tagimalek H, Khatami H. Experimental investigation joining al 5083 and high-density polyethylen by protrusion friction stir spot welding containing nanoparticles using taguchi method. International Journal of Engineering, Transactions C: Aspects. 2022;35(6):1144-53. 10.5829/ije.2022.35.06c.06
  24. Alassery F, Khan AI, Shaik MS. Implementation of Advanced Tunnel Field Effect Transistor (DP-TFET) for High Power Switching Applications. Silicon. 2022;14(15):9589-93. https://doi.org/10.1007/s12633-021-01647-7
  25. Sahu SA, Goswami R, Mohapatra S. Characteristic enhancement of hetero dielectric DG TFET using SiGe pocket at source/channel interface: proposal and investigation. Silicon. 2020;12(3):513-20. https://doi.org/10.1007/s12633-019-00159-9
  26. Balaji B, Srinivasa Rao K, Girija Sravani K, Bindu Madhav N, Chandrahas K, Jaswanth B. Improved drain current characteristics of hfo2/sio2 dual material dual gate extension on drain side-tfet. Silicon. 2022;14(18):12567-72. https://doi.org/10.1007/s12633-022-01955-6
  27. Kumar PK, Balaji B, Rao KS. Halo-Doped Hetero Dielectric Nanowire MOSFET Scaled to the Sub-10 nm Node. Transactions on Electrical and Electronic Materials. 2023:1-11. https://doi.org/10.1007/s42341-023-00448-6
  28. Emami N, Kuchaki Rafsanjani M. Extreme learning machine based pattern classifiers for symbolic interval data. International Journal of Engineering, Transactions B: Applications. 2021;34(11):2545-56. 10.5829/IJE.2021.34.11B.17
  29. Fouladinia F, Gholami M. Decimal to excess-3 and excess-3 to decimal code converters in QCA nanotechnology. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1618-25. 10.5829/ije.2023.36.09c.05
  30. Gowthami Y, Balaji B, Rao KS. Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device. Journal of Electronic Materials. 2023;52(4):2561-8. https://doi.org/10.1007/s11664-023-10217-z
  31. Rani CSH, Bagan KB, Roach RS. Improved drain current characteristics of germanium source triple material double gate hetero-dielectric stacked TFET for low power applications. Silicon. 2021;13:2753-62. https://doi.org/10.1007/s12633-020-00556-5
  32. Mehrabani AH, Fattah A, Rahimi E. Design and Simulation of a Novel Hetero-junction Bipolar Transistor with Gate-Controlled Current Gain. International Journal of Engineering, Transactions C: Aspects. 2023;36(03):433. 10.5829/ije.2023.36.03c
International Journal of Engineering
Volume 37, Issue 3
TRANSACTIONS C: Aspects
March 2024
Pages 520-528

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