Graph Centrality Algorithms for Hardware Trojan Detection at Gate-Level Netlists

Document Type : Original Article

Authors

1 School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran

2 Department of Computer Engineering, Sharif University of Technology, Tehran, Iran

Abstract

The rapid growth in the supply chain of electronic devices has led companies to purchase Intellectual Property or Integrated Circuits from unreliable sources. This dispersion in the design to fabrication stages of IP/IC has led to new attacks called hardware Trojans. Hardware Trojans can bargain information, reduce performance, or cause failure. Various methods have been introduced to detect or prevent hardware Trojans. Machine learning methods are one of these. Selecting the type and number of input variables in the learning algorithm has an important role in the performance of the learning model. Some previous hardware Trojan detection studies have used structural gate-level features to create data sets for machine learning models. In this paper, a method based on directed graphs for extracting features is proposed. The proposed method use Graph Centrality Algorithm and structural gate-level features. To examine the importance and the impact of the extracted features with the proposed method, three types of data sets are created as input to the learning model made with XGBoost. The trained learning models based on these three data sets show that extracting graph-based features has improved the F1-score by 10% and the ROC by 22%. The combination of these features with the structural gate-level features improved the F1-score by 17.5% and the ROC by 38.5%.

Keywords

Main Subjects

References

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International Journal of Engineering
Volume 35, Issue 7
TRANSACTIONS A: Basics
July 2022
Pages 1375-1387

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