Elect & Computer Engineering, Babol Nooshirvani University of Technology
Electrical & Electronic Engineering, University of Mazandaran
Electrical & Computer Engineering, University of Tehran, College of Engineering
Computer & Electrical Engineering, Babol Noshiravani University of Technology
Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of each delay cells. Since this novel architecture has removed phase detector, charge pump and loop filter, the proposed structure shown occupy smaller chip area and has less settling time than conventional DLLs. This method could be implemented in a real system by means a digital signal processor device. Simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulations, the proposed architecture has locking time approximately 286nsec which is equal to 4 clock cycles of reference clock.