ICT, Gautam Buddha University
Information Technology, Gautam Buddha University
Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to be a huge researched outcome for its easy realizability in on-chip design in the field of vector rotated DSP applications. In this paper we propose a pipelined CORDIC architecture for digital demodulation in high performance, low power frequency modulated CW Radar. A complex Digital Phase Locked Loop (DPLL) has been used for digital demodulation with pipelined CORDIC module as its core processing element. The FPGA implementation of CORDIC based design has been chosen because of its inherent high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. Substantial amount of resource utilization has been reduced in proposed design. For better loop performance of first order complex DPLL during demodulation, the convergence of the CORDIC architecture is also optimized. Multiplierless BOXCAR filter has been incorporated at the final stage of the design for better information recovery from narrow samples with little energy signal and easy realization. Hardware synthesized result using Cadence design tools are presented.