A Fault Tolerant Operation of 3-Phase, 5-Level CHBMLI under Open Circuit Fault Conditions

Fault detection and its restoration is the major challenge for the smooth functioning of the Multi-Level Inverter (MLI). In this paper, fault detection and its clearance scheme for an Open Circuit (OC) fault on a 3-level 5-level Cascaded H-Bridge Multi-Level Inverter (CHBMLI) has been developed and tested to improve the reliability and suitability of the system. An accurate and fast detection, isolation and bypassing of faulty bridges enhance the reliability, suitability, and acceptability of CHBMLI in any domestic, industrial drive applications. To reschedule the line voltage and current value close to the pre-fault level, a Neutral Point Shift (NPS) technique is presented in this paper. The desired output voltage is governed by Level Shift Pulse Width Modulation (LSPWM) technique. The proposed scheme is developed in MATLAB/Simulink environment and results are validated by using Opal-RT simulator. Simulation results has confirmed the performance and Opal-RT simulator results shows feasibility and applicability of the proposed scheme.


INTRODUCTION 1
Multilevel Inverters (MLI) are widely accepted in all industrial, domestic, and electric power grid utility systems to improve the sustainability and reliability of the overall system [1].Due to increasing penetration of renewable energy sources such as wind power and PV solar power, the importance of MLI has increased [2,3].
The MLI has various advantages such as low voltage stress (dv/dt) across switches, low Total Harmonic Distortion (THD) of output ac voltages, low rating of IGBT switches and providing effective performance by *Corresponding Author Email: rkkumarr68@gmail.com(R. Kumar) conventional power electronics inverters [4,5].Because of their exclusive merits, the MLI is being used in various applications like v/f control in drive systems, HVDC transmission systems [6,7].Many topologies of MLI are available with different switch combinations and source arrangements.Some of the standard multilevel inverter topologies are further subclassified as: Flying Capacitors/Capacitor Clamped MLI (FCMLI), Neutral Point Clamped/Diode Clamped Multi-Level Inverter (NPCMLI), and Cascaded H-bridge MLI (CHBMLI), and their comparison is given in Table 1 [8,9].The CHBMLI is one of the most effective and popular topology.The advantage of CHBMLI is that, if any bridge is faulty, it bypasses the faulty bridge and provides continuous supply from other bridges.Since the CHBMLI requires separate DC sources, hence, it is suitable for several renewable energy sources like wind, PV, and fuel cells as shown in Figure 1.It is also suitable for medium voltage, high power distribution, Battery Energy Storage Systems (BESS), and industrial drives due to a high degree of modularity and high voltage ridethrough [10,11].In CHBMLI, the number of levels in output voltage increases with an increase in the number of bridges.So, the reliability of the inverter depends on the number of components present in the system.Due to the large number of semiconductors i.e., IGBT switches in MLI, the chances of failures in components increase which tends to create Open-Circuit (OC) and  Short-Circuit (SC) faults [12,13].The fault in the gate terminal in IGBT switches is considered as an OC fault.
The switch fault count is approximately 1/3 rd of the total fault in power converters.The OC fault in any switch of CHBMLI bridge leads to unbalanced load, and voltage disturbed.This creates unbalancing in output current and voltage, which increases the chances of other devices failure and may lead to the system collapse.The distribution of faults due to failure of components such as PCB 26%, capacitor 30%, semiconductor devices 21%, solder joint 13%, conductor 3%, and other 7% in power electronics converters is shown in Figure 2 [14].
In this paper, the comparative analysis of the OC fault detection methods, fault detection time, and their parameters are discussed.Sim et al. [15] detected the OC fault of CHBMLI based on output current waveform and zero voltage switching states, the detection time for identifying the faulty switch takes more than 40 msec.
Here, the performance of detection is poor for faulty switch identification.The method presented by Faraz et al. [16] is based on a sliding mode observer to detect the In the fault detection method given by Anand et al. [17], the mean output bridge voltage is taken as detection parameter.The OC fault was detected for CHBMLI by comparing the half-cycle mean value of bridges voltage (HCMV) with normal operating mean output voltage.It can detect faulty switch of CHBMLI within 20 msec with LSPWM.The OC switch fault detection for T-Type MLI is given by He et al. [18].In this method, the output current of MLI compares with online data which is already trained for OC fault in different conditions.This technique requires a set of data; due to this, it takes more than 20 msec for the execution of data for each healthy bridge.Thantirige et al. [19] presented the fault detection which is based on FFT analysis of phase current signal to detect faulty bridge.The fault is detected in less than 100 msec, this technique detects only faulty cell.This operation takes 60 msec to check the data in each step and this method also requires data training [20].The accuracy is less under light load conditions.In the method given by Lezana et al. [21], fault detection is done based on output voltage switching frequency analysis for a cascaded multicell converter.The operation of fault detection is implemented by high frequency harmonic analysis.The behavior of fault is predicted under the approximate method.It takes more than 30 msec to implement this technique.A gravitational search algorithm is implemented to detect the OC fault for the cascaded half-bridge MLI [22].This detection technique takes 20 msec for fault detection operation.It is for the limited number of switches and it does not give clear identification of faulty switches, since it is an approximate method.The generation of balanced threephase line voltages and currents is described by Deepak and Das [23].This is achieved by adjusting the threephase angles with reference signals given to each leg of the inverter.The fault tolerance of MLI is implemented by the neutral point shift (NPS) technique to maximize the available voltage after bypassing the faulty bridge [24].The fault is tolerated to improve overall system reliability.Research work is carried out in this concern to enhance the performance of the semiconductor switch with reliable operation.The main contributions of this paper are as follows: • The developed algorithm based on instantaneous paramerters for fault detection and inherent isolation of the faulty bridge with minimum fault detection time.• The neutral point shift (NPS) technique is implemented for fault-tolerant operation under OC faults on the switches to ensure uninterrupted, and reliable supply to the load.
• The proposed algorithm is implemented in MATLAB/Simulation and validated through the real-time simulator Opal-RT.In section 2, the Cascaded H-bridge (CHB) 5-level inverter and PWM techniques are discussed.The analysis of fault detection and fault-tolerant NPS technique and OC fault detection in 3-phase, 5-level CHBMLI are addressed in section 3. Section 4 deals with the simulation results under different operating conditions.The Opal-RT simulator results are described in section 5. Conclusion of the proposed work is in section 6.

CASCADED H-BRIDGE 5-LEVEL INVERTER
The conventional power electronic inverters produce only two voltage levels either +Vdc or -Vdc , but the CHBMLI generates an expected sinusoidal output voltage from several DC input voltage sources.It consists of a series connections of n-bridges.Each bridge gives three output voltage levels as +Vdc, 0, and -Vdc obtained by implementing the different switching patterns [25].The switching sequence and output voltages under normal operating condition is shown in Table 2.In symmetric cascaded H-bridge multilevel inverter, to get m-number of levels in output voltage, it requires 2*(m-1) switches, (m-1)/2 number of DC sources or number of Hbridges per phase leg, and switch blocking voltage is 2*(m-1) [26].The sum of all the bridge output voltages gives the phase voltage.In this paper, for obtaining the 5level, two H-bridges are connected in series in each phase as shown in Figure 1.i.e., (VAN =VH1 +VH2).The phase output voltages of MLI is given by: {   =   *  *   sin()   =   *  *   sin( − 120 0 )   =   *  *   sin( + 120 0 ) (1) The phase output magnitude with n-bridges; The commonly used PWM techniques are Level Shift PWM (LSPWM) and Phase Shift PWM (PSPWM).These methods are simple and used in various topologies than space vector PWM.In LSPWM, all carrier signals have the same frequency and peak-to-peak amplitude. .
In PSPWM, the carrier signals are phase-shifted from one another, with the same frequency and peak-to-peak amplitude.An MLI with 'm' output voltage levels, (m-1) triangular carrier signals are required, whichare shifted by an angle (θcr).The comparison between PSPWM and LSPWM techniques is shown in Table 3.

ANALYSIS OF FAULT DETECTION AND FAULT TOLERANT
Internal faults of the CHBMLI, such as the OC and SC faults are major faults.The internal short-circuit (SC) faults occur in IGBT, mainly due to the drastic increase in temperature.The peak current flows through collector

1. Open-Circuit (OC) Fault Detection
The opencircuit fault may occur on any switch, which creates an unbalance in the output voltages and currents.This leads to disturbance in the CHBMLI system.If the disturbance persists, the system will be shutdown.To avoid complete shutdown of the system, the algorithm proposed for fault detection and fault-tolerant techniques are implemented.An accurate and fast fault detection, inherent fault isolation, and bypassing of the faulty bridge ensure the reliability, suitability, and acceptability of CHBMLI in any domestic, industrial drive applications.
During OC fault, in any IGBT switch, the bridge voltage, current, and its magnitude deviates from normal operating condition with constant DC input.The fault detection in bridges is based on the monitoring of instantaneous bridge output voltage (vH1, vH2) and instantaneous output current (iA).The faulty bridge, the faulty switch is identified by comparing the voltage across diagonal switches of each bridge and the instantaneous output current using fault detection algorithm.The proposed scheme for fault detection in 3phase 5-level CHBMLI with fault-tolerant NPS technique is shown in Figure 3.For getting the optimality with minimum trade-off, all the possible OC fault conditions have been considered in the proposed

2. Faulty Condition
For five levels of CHBMLI, each phase consisting two bridges.Under balance condition, there are two isolated neutral points one is the inverter neutral point (Pn) and the other is the load neutral point (N ), both of them are at the same potential as shown in Figure 8 (a) and (b).In this figure, all bridges (A1, A2, B1, B2, C1, C2) are healthy, hence the line voltages VAB, VBC, VCA are balanced and form an equilateral triangle with 120 0 phase displacement.When there is a fault at 2 nd bridge of phase-A, bridge-A2 is isolated from the system as shown in Figure 9(a).Hence the line voltages VAB, VCA are disturbed, resulting in unbalance of voltages.

Fault Tolerant
The simple fault tolerant technique described in literatures are: (I) if there is OC fault at bridge-A2 of phase-A, bypass or deactivate all its counterparts or same number of bridges from the other healthy phases (i.e., from phase-B, bridge-B2, and from phase-C, bridge-C2) to maintain system balanced as shown in Figure 9 (b) [23], so that each phase will have one healthy bridge.However, deactivating the healthy bridge reduce the utilization of the DC-link voltage.This practice is not advisable.(II) Increase the input DC voltage of healthy bridges i.e., if bridge-A2 has a fault, then increase the voltage of bridge-A1 to 2Vdc to compensate the loss of bridge-A2.
But this leads to increase in voltage stress on the switches.So, increasing the input DC voltage to healthy bridge is also one of the drawbacks.The neutral point shift method is used to overcome these drawbacks,

4. Neutral Point Shift (NPS) Technique
The fault-tolerant operation of CHBMLI ensure the continuous operation of the system during and after the fault conditions.The fault-tolerant NPS technique is implemented to balance and maximize the available output line voltages and currents after bypassing the faulty bridge [27].Normal operating condition, both the neutral points (inverter neutral and load neutral) are at the same potential, and output phase voltages (VAN, VBN, VCN) of CHBMLI are balanced.All phase voltages are displaced by 120 0 and form an equilateral triangle by joining line voltages (VAB,VBC, VCA).If OC fault occurs on bridge-H2 of phase-A, only bridge-H1 of phase-A contributes to the phase voltage (VAN).This reduces the magnitude of phase voltage which results in unbalanced output line voltages.The magnitude of line voltage VAB and VCA are less than VBC.The phase voltages (VAN,VBN, VCN) changes to new phase voltages as L1, L2, and L3 respectively.To maintain the output line voltages and currents balanced, the neutral point of CHBMLI (Pn) is shifted toward a new neutral point (  ′ ) without disturbing other healthy bridges.The shifting of inverter neutral point (  ′ ) due to OC fault creates new balanced line voltages 'a'.The new output line voltages form a new equilateral triangle with reduced magnitude than the prefault condition.The coordinates (x, y) representation of 3-phase, 5-level CHBMLI with a fault in phase-A of new line voltage 'a' and new phase shift angle (α, β, γ) is shown in Figure 10.
Let (x, y) be the coordinates of new inverter neutral point   ′ ; 2 2 = ( − ) 2 +  2 (4) Putting the Equations ( 4) and ( 5) in Equation ( 3), then the new line voltage 'a' is obtained as: Here, To meet the Equations ( 3)-( 7), the following condition must be satisfied: After the calculation of new line voltage 'a', new phase angles are calculated as: From Equation ( 6), the value of new voltage 'a' depends on Lx and Ly , + sign gives maximum of 'a' and sign give minimum value of 'a'.After the detection of a fault, the bridge is bypassed and the modulating signal with all three phase angles given by Equation 9is generated in a controller, and PWM is implemented.The schematic block diagram of the proposed algorithm for fault detection and fault-tolerant along with LSPWM control for the IGBT switch is shown in Figure 11.It consists of D.C source, 3-phase, 5-level CHBMLI, controller, and load.The controller consists of a fault detection technique to detect the fault, and the NPS technique is implemented to control the modulating signal for fault-tolerant, and reassign the modulating signal (i.e.,VAref, VBref, VCref).The generated modulating signals are compared with the multicarrier triangular signal (i.e., LSPWM) and gate pulses are generated to operate MLI.

RESULTS AND DISCUSSION
The parameters used for simulation of 3-phase, 5-level CHBMLI with a star-connected RL-load is shown in Table 4.The results are verified with real-time Opal-RT simulator.The LSPWM technique is used for the generation of gate pulses for CHBMLI.The fault detection algorithm is implemented to detect the OC fault.The operation of the proposed method for fault detection and tolerance is studied for all the cases where as; results for case III and case IV with bridge-H2 are presented here.In these cases, the fault detection technique senses the instantaneous phase current, instantaneous bridge voltage and instantaneous voltage across switches.Based on the condition corresponding to faulty switch is identified and bypassed for secure and reliable operations.This method detects and tolerates the faulty switch of any phase of the system and, maintains the line voltage and current in balanced condition with the desired magnitude.In case III, an OC fault is created on switch Sa21 in bridge-H2 of phase-A, at 0.041s, where the output phase voltage (VAN) and bridge-H1 output voltage (vH1) are shown in Figure 12  The fault detection signal goes high at 0.042s thus; the fault which was created at 0.041s is detected at 0.042s.This shows that, in this case the fault detection time is 1 msec.Similarly, in case IV, an OC fault is created on Sa23 in bridge-H2 of phase-A at 0.041s, where the output phase voltage (VAN) and bridge-H1 output voltage (vH1) are plotted in Figure 13   During normal operating condition, the rms value of the line voltages and the THD is 400 V, 17% respectively as shown in Figure 16.But, during OC fault, the observed rms values of voltage and percentage of THD are different.The rms values of line voltage (VAB) is 326 V and THD is 22%, for VBC it is 400 V and THD is 17%, and for VCA it is 326 V and THD is 23%, as shown in Figure 17.During post fault and after implementation of NPS, the line voltages and currents are balanced with rms value of 343 V and THD = 20%, as shown in Figure 18.
Thus, the results obtained from simulation validates performance of proposed technique for fault detection, inherent isolation capability, and fault tolerant operation.

OPAL-RT SIMULATOR AND REAL TIME RESULTS
The  6.This comparison shows that the proposed algorithm has least fault detection time and provides fault-tolerant operation also.Thus, this algorithm is useful in supplying uninterrupted power to critical loads.

Figure 2 .
Figure 2. Faults percentages due to failure of devices in converters For an MLI with 'm' voltage levels, (m-1) triangular carrier signals are required.The carrier signals are disposed over one another.In this paper, the level-shift pulse width modulation (LSPWM) technique is used to control the switching pattern to maintain the desired output voltage.The amplitude (ma) and frequency (mf) modulation index are given as,   =     (−1) and   =

Figure 3 .Figure 4 .Figure 5 .
Figure 3. Flow chart for fault detection and fault tolerant with NPS

Figure 10 .
Figure 10.Coordinates representation for parameters calculations

Figure 11 .
Figure 11.Block diagram of proposed control scheme for 3-phase, 5-level CHBMLI (a) and (b) respectively.The output voltage of bridge-H2 (vH2) is healthy up to 0.041s which; either becomes 0 or -Vdc during fault condition as seen in Figure 12 (c).The change in phase current (iA) during normal to the faulty condition is observed in Figure 12 (d).The voltage across switch Sa24 (v_Sa24), gate pulse signal for Sa21, and the fault detection signal are shown in Figure 12 (e), (f), and (g) respectively.
(a) and (b) respectively.Due to fault on Sa23, the bridge-H2 output voltage (vH2) is either 0 or +Vdc as shown in Figure 13 (c).The change in current (iA) during OC fault and voltage across switch (v_Sa22) are also shown in Figure 13 (d) and (e) respectively.The gate pulse signal for Sa23 and the fault detection signal are shown in Figure 13 (f), and (g), respectively.

TABLE 2 .
Switching sequence and output voltage level of 5levels CHBMLI

TABLE 3 .
Comparison between level-shift and phase-shift sinusoidal PWM IGBT, without gate pulse, due to continuous increase in voltage beyond breakdown.The OC fault occurs due to open gate terminal or improper connection of collector and emitter terminal.In this paper, a fault detection algorithm is developed for 3-phase, 5-level CHBMLI to detect the fault under OC condition.