Design and Simulation of a Novel HBT Transistor with Gate-Controlled Current Gain

Document Type : Original Article

Authors

1 Electrical Engineering Department, Shahrood University of Technology, Shahrood, Iran.

2 Electrical Engineering Department, Shahrood University of Technology, Shahrood, Iran

3 Shahrood University of Technology

Abstract

Abstract: A new structure for SiGe HBT transistor is designed and simulated using Silvaco simulator. The considered extra terminal gives the ability to control the transistor's current gain. By applying voltage to the Gate terminal, the Base effective width would be controlled. Decrement of the Base width yields to the carrier recombination rate reduction, let the emitted electrons to have higher chance to reach the Collector. Considering extra terminal have two approaches. One is to improve the current gain of the transistor by applying a constant voltage to the Gate and the other is to modify the characteristics of the transistor in such a way that the current gain became optimized. The current gain of the transistor without any Gate voltage is about 50, which increases to 750 for high and 50,000 for low collector currents with the Gate voltage variation consideration. In addition, our final proposed Gate-Controlled HBT with a large gate over the base and collector has the breakdown voltage of 8V and the cut-off frequency of about 11 GHz. The maximum FoM of 1200 is achieved using the proposed structure.

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