Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

Document Type : Original Article

Authors

1 Aviation Electronics Department, Civil Aviation Technology College, Tehran, Iran

2 Aviation Electronics Laboratory, Civil Aviation Technology College, Tehran, Iran

Abstract

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

Keywords


  1. Hosticka, B. J. “Improvement of the Gain of CMOS Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 14, No. 6, (1979), 1111-1114. DOI: 10.1109/JSSC.1979.1051324
  2. Bult K. & Geelen G. “A Fast-Settling CMOS Operational Amplifier for SC Circuits with 90-dB DC Gain”, IEEE J. of Solid-State Circuits, Vol. 25, No 6, (1990), 1379-1384. DOI: 10.1109/4.62165.
  3. Chiu, Y. “On the Operation of CMOS Active-Cascode Gain Stage”, Journal of Computer and Communications, Vol. 1, No. 6, (2013), 18-24. DOI: 10.4236/jcc.2013.16004.
  4. Das, M. “Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 3, (2002), 204-207. DOI: 10.1109/TCSII.2002.1013867.
  5. Razavi, B., Design of Analog CMOS Integrated Circuits. Second Edition. New York, NY:McGraw-Hill, 2016.
  6. Zhang, S., Zhu, Z., Zhang, H., Xiong, Z. and  Li, Q. “A 90-dB DC gain high-speed nested gain-boosted folded-cascode opamp”, 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Glasgow, UK, 2015, 357-360, doi: 10.1109/PRIME.2015.7251409.
  7. Assaad R. S. &. Martinez S. “The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, (2009), 2535-2542. DOI: 10.1109/JSSC.2009.2024819.
  8. Akbari M. & Hashemipour O. “A super class-AB adaptive biasing amplifier in 65-nm CMOS technology”, International Journal of Electronics Letters, Vol. 6, No. 3, (2018), 302-314. DOI: 10.1080/21681724.2017.1376710.
  9. Garde M. P., Lopez-Martin, Carvajal A. & Ramírez-Angulo J. “Super Class-AB Recycling Folded Cascode OTA”, IEEE Journal of Solid-State Circuits, Vol. 53, No. 9, (2018), 2614-2623. DOI: 10.1109/JSSC.2018.2844371.
  10. Lopez-Martin, A., Grade, M. P., Algueta, J. M., Cruz Blus, C. A., Carvajal, R. G. & Ramirez-Angulo, J. “Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads”, IEEE  J. of Trans. on Circuits and Syst._II, Express Brief, Vol. 65, No. 4, (2018), 441-445. DOI: 10.1109/TCSII.2017.2700060.
  11. MiarNaimi, H. and Fallah, M. “A Novel Low Voltage, Low Power and High Gain Operational Amplifier Using Negative Resistance and Self Cascode Transistors”, International Journal of Engineering, Transactions C: Aspects, Vol. 26, No.3, (2013), 303-308.
  12. Hashemipour, O. and Ghorvanchi, P. (2004). “A Very Low Voltage 9TH Order Linear Phase Baseband Switched Capacitor Filter” International Journal of Engineering, Transactions A: Basics, Vol. 17, No. 1, (2004), 19-24.
  13. Rashtian, M., Hashemipour, O., Navi, K., Jalali, A. “A Novel Structure for Realization of a Pseudo Two Path Band-Pass Filter”. International Journal of Engineering, Transactions B: Applications, Vol. 23, No. 3, (2010), 201-208.
  14. Garcia-Alberdi, C., Lopez-Martin, A. J., Acosta, L., Carvajal, R. G.  & Ramirez-Angulo, J. “Tunable Class AB CMOS Gm-C Filter Based on Quasi-Floating Gate Techniques”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 5, (2013), 1300-1309. DOI: 10.1109/TCSI.2012.2220504.
  15. Mesri, A., Pirbazari, M. M, Hadidi, K. and Khoei, A. “High gain two-stage amplifier with positive capacitive feedback compensation”, IET Journal of Circuits, Devices and Systems, Vol. 9, No. 3, (2015), 181-190. DOI: 10.1049/iet-cds.2014.0139.
  16. Joshi, A., Shrimali, H., Sharma and S. K. “Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor”, IET Journal of Circuits, Devices and Systems, Vol.  11, No. 3, (2017), 225-231. DOI: 10.1049/iet-cds.2016.0448.
  17. Ju, H. and Lee, M. “A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 8, (2020), 1770-1781. DOI: 10.1109/TVLSI.2020.2986508.