An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

Document Type : Original Article


School of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran


In this paper, an enhanced self-checking carry select adder (CSeA) architecture is introduced. However, we first show that the carry select adder design presented literature does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.


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