1. Giacomotto, C., Singh, M., Vratonjic, M. and Oklobdzija, V.G., “Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements”, Lecture Notes in Computer Science, Vol. 5349, (2009), 268-276.
2. Leverich, J., Monchiero, M., Talwar, V., Ranganathan, P. and Kozyrakis, C., "Power management of datacenter workloads using per-core power gating", IEEE Computer Architecture Letters, Vol. 8, No. 2, (2009), 48-51.
3. Pakbaznia, E. and Pedram, M., "Design and application of multimodal power gating structures", in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, IEEE., (2009), 120-126.
4. Mistry, J.N., Al-Hashimi, B.M., Flynn, D. and Hill, S., "Sub-clock power-gating technique for minimising leakage power during active mode", in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, IEEE., (2011), 1-6.
5. Nath, D., Choudhury, P., Nag, A. and Pradhan, S.N., "Power gating architecture implementation inside clock period to reduce power", International Journal of Computer Aided Engineering and Technology 5, Vol. 6, No. 3, (2014), 310-323.
6. Kim, S., Choi, C.J., Jeong, D.-K., Kosonocky, S.V. and Park, S.B., "Reducing ground-bounce noise and stabilizing the data-retention voltage of power-gating structures", IEEE transactions on Electron Devices, Vol. 55, No. 1, (2008), 197-205.
7. Singh, R., Kim, A., Kim, S. and Kim, S., "A three-step power-gating turn-on technique for controlling ground bounce noise", in Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, ACM., (2010), 171-176.
8. Singh, R., Woo, J.-K., Lee, H., Kim, S.Y. and Kim, S., "Power-gating noise minimization by three-step wake-up partitioning", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 59, No. 4, (2012), 749-762.
9. Kumar, Y., Paliwal, S., Rai, C.K. and Balasubramanian, S., "A novel ground bounce reduction technique using four step power gating", in Engineering and Systems (SCES), 2013 Students Conference on, IEEE., (2013), 1-5.
10. Kim, S., Kosonocky, S.V., Knebel, D.R., Stawiasz, K. and Papaefthymiou, M.C., "A multi-mode power gating structure for low-voltage deep-submicron cmos ics", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 7, (2007), 586-590.
11. Chowdhury, M.H., Gjanci, J. and Khaled, P., "Controlling ground bounce noise in power gating scheme for system-on-a-chip", in Symposium on VLSI, 2008. ISVLSI'08. IEEE Computer Society Annual, IEEE., (2008), 437-440.
12. Jiao, H. and Kursun, V., "Ground-bouncing-noise-aware combinational mtcmos circuits", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 8, (2010), 2053-2065.
13. Jiao, H. and Kursun, V., "Ground bouncing noise suppression techniques for data preserving sequential mtcmos circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, (2011), 763-773.
14. Saxena, C., Pattanaik, M. and Tiwari, R., "Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits", in Devices, Circuits and Systems (ICDCS), 2012 International Conference on, IEEE., (2012), 239-243.
15. Sreenivasulu, P. and Rao, K.S., "Ground bouncing noise reduction in combinational mtcmos circuits", in Communication and Network Technologies (ICCNT), 2014 International Conference on, IEEE , (2014), 270-275.
16. Talwekar, R. and Jain, N.B., "Enhanced ground bounce noise reduction in low leakage cmos multiplier cell", in Research Advances in Integrated Navigation Systems (RAINS), International Conference on, IEEE., (2016), 1-6.
17. Kumar, Y., Paliwal, S., Sahu, P. and Balasubramanian, S., "Ground bounce noise minimization using multi-vdd level converter", in Electronics, Computing and Communication Technologies (IEEE CONECCT), 2014 IEEE International Conference on, IEEE., (2014), 1-4.
18. Wu, Q., Li, W., Li, N. and Ren, J., "A 1.2 v 70 ma low drop-out voltage regulator in 0.13 µm cmos process", in ASIC (ASICON), 2011 IEEE 9th International Conference on, IEEE., (2011), 978-981.
19. Hicham, A. and Qjidaa, H., "A 500μa low drop-out voltage regulator in 90-nm cmos technology", in Complex Systems (ICCS), 2012 International Conference on, IEEE., (2012), 1-4.
20. Kugelstadt, T., "Fundamental theory of pmos low-dropout voltage regulators", Texas Instruments Application Report, (1999), 1-6.
21. Giustolisi, G., Palumbo, G. and Spitale, E., "Robust miller compensation with current amplifiers applied to ldo voltage regulators", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 59, No. 9, (2012), 1880-1893.
22. Torres, J., El-Nozahi, M., Amer, A., Gopalraju, S., Abdullah, R., Entesari, K. and Sanchez-Sinencio, E., "Low drop-out voltage regulators: Capacitor-less architecture comparison", IEEE Circuits and Systems Magazine, Vol. 14, No. 2, (2014), 6-26.
23. Kim, S., Kosonocky, S.V. and Knebel, D.R., "Understanding and minimizing ground bounce during mode transition of power gating structures", in Proceedings of the 2003 international symposium on Low power electronics and design, ACM., (2003), 22-25.
24. ISCAS89. Sequential benchmark circuits.
25. Lee, B.S., "Technical review of low dropout voltage regulator operation and performance", Application Report........ slva072, (1999).
26. Jeong, K., Kahng, A.B., Kang, S., Rosing, T.S. and Strong, R., "Mapg: Memory access power gating", in Proceedings of the Conference on Design, Automation and Test in Europe, EDA Consortium., (2012), 1054-1059.
27. Kahng, A.B., Kang, S. and Park, B., "Active-mode leakage reduction with data-retained power gating", in Proceedings of the Conference on Design, Automation and Test in Europe, EDA Consortium., (2013), 1209-1214.