An Accurate 2D Analytical Model for Transconductance to Drain Current ratio (gm/Id) for a Dual Halo Dual Dielectric Triple Material Cylindrical Gate All Around MOSFETs


Amity University Haryana, Gurugram, India


A dual-halo dual-dielectric triple-material cylindrical-gate-all-around/surrounding gate (DH-DD-TM-CGAA/SG) MOSFET has been proposed and an analytical model for the transconductance-to-drain current ratio (TDCR) has been developed. It is verified that incorporation of dual-halo with dual-dielectric and triple-material results in enhancing the device performance in terms of improved TDCR. The effect on TDCR is analyzed for variations in device parameters like oxide thickness, silicon thickness, channel doping concentration, channel length and drain bias.The results show that larger value of gm/Id can be obtained in proposed device in comparison to other existing triple material structures which makes it suitable for micropower applications. The analytical results of the developed gm/Id model strongly agrees with the simulated results obtained from TCAD Silvaco.


1.     Park, J.-T. and Colinge, J.-P., "Multiple-gate soi mosfets: Device design guidelines", IEEE Transactions on Electron Devices,  Vol. 49, No. 12, (2002), 2222-2229.

2.     Kumar, M.J., Orouji, A.A. and Dhakad, H., "New dual-material surrounding gate nanoscale mosfet: Analytical threshold-voltage model", IEEE Transactionson Electron Devices,  Vol. 53, No. 4, (2006), 920-923.

3.     Chiang, T., Chen, M. and Wang, H., "A new two-dimensional model for dual material surrounding-gate (DMSG) mosfet's", in Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on, IEEE. (2007), 597-600.

4.     Balamurugan, N., Sankaranarayanan, K. and John, M.F., "2d transconductance to drain current ratio modeling of dual material surrounding gate nanoscale soi mosfets", Journal of Semiconductor Technology and Science,  Vol. 9, No. 2, (2009), 110-116.

5.     Niaraki, R. and Nobakht, M., "A sub-threshold 9t static random-access memory cell with high write and read ability with bit interleaving capability", International Journal of Engineering-Transactions B: Applications,  Vol. 29, No. 5, (2016), 630-636.

6.     Karimi, G. and Shirazi, S., "Ballistic (n, 0) carbon nanotube field effect transistors' iv characteristics: A comparison of n= 3a+ 1 and n= 3a+ 2", International Journal of Engineering-Transactions A: Basics,  Vol. 30, No. 4, (2017), 516-522.

7.     Rajendran, K. and Samudra, G., "Modelling of transconductance-to-current ratio (gm/Id) analysis on double-gate soi mosfets", Semiconductor Science and Technology,  Vol. 15, No. 2, (2000), 139-144.

8.     Kranti, A., Haldar, S. and Gupta, R., "Design and optimization of vertical surrounding gate mosfets for enhanced transconductance-to-current ratio (gm/Ids)", Solid-State Electronics,  Vol. 47, No. 1, (2003), 155-159.

9.     Balamurugan, N., Sankaranarayanan, K., Amutha, P. and John, M.F., "An analytical modeling of threshold voltage and subthreshold swing on dual material surrounding gate nanoscale mosfets for high speed wireless communication", JSTS: Journal of Semiconductor Technology and Science,  Vol. 8, No. 3, (2008), 221-226.

10.   Ghosh, P., Haldar, S., Gupta, R. and Gupta, M., "Analytical modeling and simulation for dual metal gate stack architecture (DMGSA) cylindrical/surrounded gate mosfet", JSTS: Journal of Semiconductor Technology and Science,  Vol. 12, No. 4, (2012), 458-466.

11.   Wang, H.-K., Wu, S., Chiang, T.-K. and Lee, M.-S., "A new two-dimensional analytical threshold voltage model for short-channel triple-material surrounding-gate metal–oxide–semiconductor field-effect transistors", Japanese Journal of Applied Physics,  Vol. 51, No. 5R, (2012), 1-5.

12.   Dhanaselvam, P.S., Balamurugan, N. and Ramakrishnan, V., "A 2d transconductance and sub-threshold behavior model for triple material surrounding gate (TMSG) mosfets", Microelectronics Journal,  Vol. 44, No. 12, (2013), 1159-1164.

13.   Dubey, S., Santra, A., Saramekala, G., Kumar, M. and Tiwari, P.K., "An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) mosfets", IEEE Transactions on Nanotechnology,  Vol. 12, No. 5, (2013), 766-774.

14.   Dhanaselvam, P.S., Balamurugan, N., Chakaravarthi, G.V., Ramesh, R. and Kumar, B.S., "A 2d analytical modeling of single halo triple material surrounding gate (SHTMSG) mosfet", Journal of Electrical Engineering & Technology,  Vol. 9, No. 4, (2014), 1355-1359.

15.   Naveh, Y. and Likharev, K., "Modeling of 10-nm-scale ballistic mosfet's", IEEE Electron Device Letters,  Vol. 21, No. 5, (2000), 242-244.

16.   Sharifi, M. and Adibi, A., "Semiconductor device simulation by a new method of solving poisson, laplace and schrodinger equations", International Journal of Engineering,  Vol. 13, No. 1, (2000), 89-94.

17.   Gupta, N., Patel, J.K.B. and Raghav, A.K., "Modeling and analysis of threshold voltage for dual-halo dual-dielectric triple-material surrounding-gate mosfets", International Journal of Pure and Applied Mathematics,  Vol. 118, No. 18, (2018), 3759-3771.

18.   Atlas, D.S., "Atlas user’s manual", Silvaco International Software, Santa Clara, CA, USA,  (2005).

19.   Shafiabadi, M. and Mehrabani, Y.S., "Symmetrical, low-power, and high-speed 1-bit full adder cells using 32nm carbon nanotube field-effect transistors technology", International Journal of Engineering-Transactions A: Basics,  Vol. 28, No. 10, (2015), 1447-1454.