Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

Authors

Department of ECE, National Institute of Technology, Agartala. Agartala, India

Abstract

Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can minimize the number of switching activity between two successive patterns. The switching power dissipation of the Circuit under Test (CUT) also depends on the order of patterns applied for. If consecutive pattern application time is sufficiently large then leakage power dissipation does not alter on the ordering of the patterns. So under this circumstances leakage power does not change but if the pattern application time is small leakage power depends on the ordering of the pattern applied to the CUT. Previous works concerns only about don’t care filling or pattern ordering or first filling of don’t care and then ordering for low power circuit testing. Ordering after filling of don’t care may change the benefits of X-filling. The advantage of test power reduction of both the methods - don’t care filling and ordering may be obtained if they are considered together. In this work an approach based on Genetic Algorithm (GA) is used to solve the integrated problem for X-filling and reordering of test patterns considering pattern dependency to minimize the switching activity throughout testing without changing the fault coverage. Effectiveness of the proposed GA based approach compared to existing approach considering test patterns for ISCAS’85 benchmark circuits is shown in the result section.

Keywords


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