A New Circuit Scheme for Wide Dynamic Circuits

Author

School of Engineering, Damghan University, Damghan, Iran

Abstract

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in gates. Furthermore, the subthreshold leakage current is decreased by using the footer transistor in diode configuration and consequently, the noise immunity is increased in the proposed circuit. Simulation results of wide fan-in OR gates in 90nm CMOS technology demonstrate 48% power reduction and 1.65× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates.

Keywords

References

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International Journal of Engineering
Volume 31, Issue 5
TRANSACTIONS B: Applications
May 2018
Pages 699-704

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