A New Circuit Scheme for Wide Dynamic Circuits

Author

School of Engineering, Damghan University, Damghan, Iran

Abstract

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in gates. Furthermore, the subthreshold leakage current is decreased by using the footer transistor in diode configuration and consequently, the noise immunity is increased in the proposed circuit. Simulation results of wide fan-in OR gates in 90nm CMOS technology demonstrate 48% power reduction and 1.65× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates.

Keywords


1.     Rabaey, J.M., Chandrakasan, A.P. and Nikolic, B., "Digital integrated circuits, Prentice hall Englewood Cliffs,  Vol. 2,  (2002).
2.     Niaraki, R. and Nobakht, M., "A sub-threshold 9t sram cell with high write and read ability with bit interleaving capability", International Journal of Engineering,Transactions B: Applications,  Vol. 29, No. 5, (2016), 630-636.
3.     Ghorban, N.D.A., Navi, K. and Hashemipour, O., "High speed full swing current mode bicmos logical operators",  International Journal of Engineering, Transaction A: Basics, Vol. 20, No. 3, (2007), 211-220.
4.     Juneja, K., Singh, N. and Sharma, Y., "High-performance and low-power clock branch sharing pseudo-nmos level converting flip-flop",  International Journal of Engineering, Transaction C: Aspects, Vol. 26, No. 3, (2013), 315-322.
5.     Jeyasingh, R.G.D., Bhat, N. and Amrutur, B., "Adaptive keeper design for dynamic logic circuits using rate sensing technique", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 19, No. 2, (2011), 295-304.
6.     Gong, N., Wang, J. and Sridhar, R., "Variation aware sleep vector selection in dual ${rm v} _ {{{rm t}}} $ dynamic or circuits for low leakage register file design", IEEE Transactions on Circuits and Systems I: Regular Papers,  Vol. 61, No. 7, (2014), 1970-1983.
7.     Peiravi, A. and Asyaei, M., "Current-comparison-based domino: New low-leakage high-speed domino circuit for wide fan-in gates", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 21, No. 5, (2013), 934-943.
8.     Moradi, F., Cao, T.V., Vatajelu, E.I., Peiravi, A., Mahmoodi, H. and Wisland, D.T., "Domino logic designs for high-performance and leakage-tolerant applications", Integration, the VLSI Journal,  Vol. 46, No. 3, (2013), 247-254.
9.     Asyaei, M., "A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology", Integration, the VLSI Journal,  Vol. 51, (2015), 61-71.
10.   Nasserian, M., Kafi-Kangi, M., Maymandi-Nejad, M. and Moradi, F., "A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic or gates", Integration, the VLSI Journal,  Vol. 52, (2016), 129-141.
11.   Asyaei, M. and Ebrahimi, E., "Low power dynamic circuit for power efficient bit lines", AEU-International Journal of Electronics and Communications,  Vol. 83, (2018), 204-212.
12.   Mahmoodi-Meimand, H. and Roy, K., "Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style", IEEE Transactions on Circuits and Systems I: Regular Papers,  Vol. 51, No. 3, (2004), 495-503.
13.   Alioto, M., Palumbo, G. and Pennisi, M., "Understanding the effect of process variations on the delay of static and domino logic", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 18, No. 5, (2010), 697-710.
14.   Asyaei, M., "A new low-power dynamic circuit for wide fan-in gates", Integration, the VLSI Journal,  Vol. 60, No., (2018), 263-271.
15.   Wang, J., Wu, W., Gong, N. and Hou, L., "Domino gate with modified voltage keeper", in Quality Electronic Design (ISQED), 2010 11th International Symposium on, IEEE. (2010), 443-446.