Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)

Authors

Department of Electronics and Communication Engineering, JNTUK, Kakinada, India

Abstract

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes more amount of power. Test circuitry is intensively used for memory testing. This may cause excessive power consumption during memory testing. Sophisticated and efficient techniques with less overhead on power must be needed. Regarding memories, power consumption is very much high during testing when compared with normal functional mode. March test algorithms are popular testing techniques used for memory testing. Power consumption during testing can be reduced by reducing the switching activity in test circuitry. A new test technique is proposed in this paper to reduce power consumption in test mode by reducing the switching activity in Built in Self-Test circuitry. Address sequencing in the address decoder is changed in such a way that it reduces switching activity.

Keywords

References

1.     Juneja, K., Singh, N. and Sharma, Y., "High-performance and low-power clock branch sharing pseudo-nmos level converting flip-flop", International Journal of Engineering-Transactions C: Aspects,Vol. 26, No.3, (2012), 315-322.
2.     Zorian, Y., "Testing the monster chip", IEEE Spectrum,  Vol. 36, No. 7, (1999), 54-60.
3.     Chandra, A. and Chakrabarty, K., "Low-power scan testing and test data compression for system-on-a-chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,  Vol. 21, No. 5, (2002), 597-604.
4.     Caşcaval, P. and Caşcaval, D., "March sr3c: A test for a reduced model of all static simple three-cell coupling faults in random-access memories", Microelectronics Journal,  Vol. 41, No. 4, (2010), 212-218.
5.     Kumar, G.R. and Babulu, K., "A novel architecture for scan cell in low power test circuitry", Procedia Materials Science,  Vol. 10, (2015), 403-408.
6.     Haniba, N.B.M., Choong, F., Reaza, M.B.I., Kamala, N. and Badala, T., "Bit swapping linear feedback shift register for low power application using 130nm complementary metal oxide semiconductor technology", International Journal of Engineering-Transactions B: Applications, Vol. 30, No. 8 (2017), 1126-1133.
7.     Kim, V.-K. and Chen, T., "On comparing functional fault coverage and defect coverage for memory testing", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,  Vol. 18, No. 11, (1999), 1676-1683.
8.     Li, J.-F., Cheng, K.-L., Huang, C.-T. and Wu, C.-W., "March-based ram diagnosis algorithms for stuck-at and coupling faults", in Test Conference, 2001. Proceedings. International, IEEE., (2001), 758-767.
9.     Gadde, P. and Niamat, M., "Fpga memory testing technique using bist", in Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on, IEEE., (2013), 473-476.
10.   Nicolici, N. and Al-Hashimi, B., "Power-constrained testing of vlsi circuits, Springer,  (2003).
11.   Niamat, M., Nemade, D. and Jamali, M., "Test, diagnosis and fault simulation of embedded ram modules in sram-based fpgas", Microelectronic Engineering,  Vol. 84, No. 2, (2007), 194-203.
12.   Bushnell, M. and Agrawal, V., "Essentials of electronic testing for digital, memory and mixed-signal vlsi circuits, Springer Science & Business Media,  Vol. 17,  (2004).
13.   Abadir, M.S. and Reghbati, H.K., "Functional testing of semiconductor random access memories", ACM Computing Surveys (CSUR),  Vol. 15, No. 3, (1983), 175-198.
14.   Dilillo, L., Girard, P., Pravossoudovitch, S., Virazel, A. and Hage-Hassan, M.B., "Data retention fault in sram memories: Analysis and detection procedures", in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, (2005), 183-188.
15.   Papachristou, C.A. and Sahgal, N.B., "An improved method for detecting functional faults in semiconductor random access memories", IEEE Transactions on Computers,  Vol., No. 2, (1985), 110-116.
16.   Suk, D.S. and Reddy, S.M., "A march test for functional faults in semiconductor random access memories", IEEE Transactions on Computers,  Vol. 12, No. C-30, (1981), 982-985.
17.   Vardanian, V.A. and Zorian, Y., "A march-based fault location algorithm for static random access memories", in On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International, IEEE. (2002), 256-261.
18.   Kaundinya, S. and Chattopadhyay, S., "Particle swarm optimization based scheme for low power march sequence generation for memory testing", in Test Symposium (ATS), 2010 19th IEEE Asian, IEEE. (2010), 401-406.
19.   Cheung, H. and Gupta, S.K., "A bist methodology for comprehensive testing of ram with reduced heat dissipation", in Test Conference, 1996. Proceedings., International, IEEE. (1996), 386-400.
20.   Kim, Y.-H., Hong, I.-S., Jung, J.-M., Kim, Y.-O. and Lim, I.-C., "An efficient test procedure for functional faults in semiconductor random access memories", Journal of Circuits, Systems, and Computers,  Vol. 1, No. 02, (1991), 229-238.
International Journal of Engineering
Volume 31, Issue 2
TRANSACTIONS B: Applications
February 2018
Pages 292-298

Files

Share

How to cite

Statistics