A Simple General-purpose I-V Model for All Operating Modes of Deep Submicron MOSFETs

Authors

Department of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran

Abstract

A simple general-purpose I-V model for all operating modes of deep-submicron MOSFETs is presented. Considering the most dominant short channel effects with simple equations including few extra parameters, a reasonable trade-off between simplicity and accuracy is established. To further improve the accuracy, model parameters are optimized over various channel widths and full range of operating voltages using a heuristic optimization algorithm. The obtained results demonstrate only 1.28% and 0.97% average error in IBM 0.13um CMOS technology for NMOS and PMOS, respectively, comparing with the accurate physically-based BSIM3 model. Furthermore, the tolerance of the model accuracy against parameters variation is investigated.

Keywords


1.     Bucher, M., Lallement, C., Enz, C.C., Théodoloz, F. and Krummenacher, F., The epfl-ekv model equations for simulation. 1998, Electronics Laboratories, Swiss Federal Institute of Technology (EPFL): Lausanne, Switzerland.

2.     Cheng, Y. and Hu, C., Mosfet modeling & bsim3 user’s guide, K.A. PUBLISHERS, Editor. 2002, KLUWER ACADEMIC PUBLISHERS.

3.     Qi, Z. and Stan, M.R., "Accurate back-of-the-envelope transistor model for deep sub-micron mos", in 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego, California., (2007), 75-76.

4.     Sakurai, T. and Newton, A.R., "Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas", IEEE Journal of Solid-State Circuits,  Vol. 25, No. 2, (1990), 584-594.

5.     Sakurai, T. and Newton, A.R., "A simple mosfet model for circuit analysis", IEEE Trans. Electron Deviees,  Vol. 38, No. 4, (1991), 887-894.

6.     Keller, S., Harris, D.M. and Martin, A.J., "A compact transregional model for digital cmos circuits operating near threshold", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  Vol. 22, No. 10, (2014), 2041-2053.

7.     Hspice® reference, manual: Mosfet models. 2010.

8.     Hamoui, A., "Current, delay, and power analysis of sublllicron cmos circuits", McGill University, Montréal, Department of Electrical and Computer Engineering, Master of Engineering,  (1998),

9.     Taherzadeh-Sani, M., Abbasian, A., Amelifard, B. and Afzali-Kusha, A., "Mos compact i-v modeling with variable accuracy based on genetic algorithm and simulated annealing", in Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on., (2004), 364-367.

10.   Fino, M.H., "A simple submicron mosfet model and its application to the analytical characterization of analog circuits", in Proceedings of the 2005 European Conference on Circuit Theory and Design. Vol. 1, (2005), I/115-I/118.

11.   Abbasian, A., Taherzadeh-Sani, M., Amelifard, B. and Afzali-Kusha, A., "Modeling of mos transistors based on genetic algorithm and simulated annealing", in 2005 IEEE International Symposium on Circuits and Systems., (2005), 6218-6221 Vol. 6216.

12.   Singh, A.K., Samanta, J. and Bhaumik, J., "Modified i-v model for delay analysis of udsm cmos circuits", in 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS), (2012), 357-360.

13.   Consoli, E., Giustolisi, G. and Palumbo, G., "An accurate ultra-compact i-v model for nanometer mos transistors with applications on digital circuits", IEEE Transactions on Circuits and Systems-I: Regular Papers,  Vol. 59, No. 1, (2012), 159-169.

14.   Yegane, B.Y., Kamalabadi, I.N. and Khanlarzade, N., "Critical path method for flexible job shop scheduling problem with preemption", International Journal of Engineering (IJE) TRANSACTIONS B: Applications,  Vol. 30, No. 2, (2017), 261-269.

15.   Samoei, P., Khodakarami, V. and Fattahi, P., "Mixed-model assembly line balancing with considering reliability", International Journal of Engineering (IJE) Transactions C: Aspects,  Vol. 30, No. 3, (2017), 411-423.

16.   Karaboga, N., An idea based on honey bee swarm for numerical optimization. 2005, Erciyes University, Engineering Faculty, Computer Engineering Department: Turkey.

17.   S. Valiollahi, R.G., A. Ebrahimzadeh, "A q-learning based continuous tuning of fuzzy wall tracking without exploration", International Journal of Engineering (IJE) Transactions A: Basics,  Vol. 25, No. 4, (2012), 355-366.

18.   Z. Guo, S.W., X. Yue, D. Jiang, K. Li, "Elite opposition-based artificial bee colony algorithm for global optimization", International Journal of Engineering (IJE) Transactions C: Aspects,  Vol. 28, No. 9, (2015), 1268-1275.

19.   Tsividis, Y., "Operation and modeling of the mos transistor., McGraw-Hill,  (1999).

20.   Langevelde, R.v. and Klaassen, F.M., "Accurate drain conductance modeling for distortion analysis in mosfets", in IEDM1997 Tech. Digest., (1997), 313-316.

21.   Comer, D.J. and Comer, D.T., "Operation of analog mos circuits in the weak or moderate inversion region", IEEE Transactions on Education,  Vol. 47, No. 4, (2004), 430-435.

22.   Gupta, K.A., Anvekar, D.K. and V, V., "Modeling of short channel mosfet devices and analysis of design aspects for power optimisation", International Journal of Modeling and Optimization,  Vol. 3, No. 3, (2013), 266-271.