Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia
Engineering, Taylors University
Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area.