Bit Swapping Linear Feedback Shift Register For Low Power Application Using 130nm Complementary Metal Oxide Semiconductor Technology (TECHNICAL NOTE)

Authors

1 Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia

2 School of Engineering and Physical Science, Heriot-Watt University, Jalan Venna, Putrajaya, Malaysia.

Abstract

Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. In this paper, an enhanced BS-LFSR for low power application is proposed. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area.

Keywords


1.     Nyathi, J., Delgado-Frias, J.G. and Lowe, J., "A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks", in Circuits and Systems, IEEE 46th Midwest Symposium on,. Vol. 3, (2003), 1384-1387.
2.     S, S. and M, T., "A low power structure design of 2d-lfsr and encoding technique for bist", International Journal of Advanced Science and Technology,  Vol. 18, (2010), 11-22.
3.     Dufaza, C., "Theoretical properties of lfsrs for built-in self test", Integration, the VLSI Journal,  Vol. 25, No. 1, (1998), 17-35.
4.     Chae, Y. and Han, G., "Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator", IEEE Journal of Solid-State Circuits,  Vol. 44, No. 2, (2009), 458-472.
5.     Fallah, M. and MiarNaimi, H., "A novel low voltage, low power and high gain operational amplifier using negative resistance and self cascode transistors", International Journal of Engineering-Transactions C: Aspects,  Vol. 26, No. 3, (2012), 303-310.
6.     Kebbati, Y., "Modular approach for an asic integration of electrical drive controls", International Journal of Engineering-Transactions B: Applications,  Vol. 24, No. 2, (2011), 107-115.
7.     Teh, Y.-K., Mohd-Yasin, F., Choong, F., Reaz, M.I. and Kordesch, A.V., "Design and analysis of uhf micropower cmos dtmost rectifiers", IEEE Transactions on Circuits and Systems II: Express Briefs,  Vol. 56, No. 2, (2009), 122-126.
8.     Farshidi, E. and Keramatzadeh, A., "A new approach for low voltage cmos based on current-controlled conveyors", International Journal of Engineering,  Vol. 27, No. 5, (2014), 723-730.
9.     Mohd-Yasin, F., Teh, Y., Choong, F. and Reaz, M., Two cmos bgr using cm and dtmost techniques. (2009), Abdus Salam International Centre for Theoretical Physics.
10.   Kamath, H.S., Nath, A., Srivastava, S.K. and Garg, S., "Comparative power analysis of lfsr test pattern generators", International Journal of Computer Applications,  Vol. 98, No. 8, (2014).
11.   Reddy, C.R.S. and Sumalatha, V., "A new built in self test pattern generator for low power dissipation and high fault coverage", in Intelligent Computational Systems (RAICS), IEEE Recent Advances in,. (2013), 19-25.
12.   Banupriya, C. and Chandrakala, S., "A low power built in repair analyzer for word oriented memories with optimal repair rate", in Green Computing Communication and Electrical Engineering (ICGCCEE), International Conference on, IEEE., (2014), 1-5.
13.   Prasanna, G.D., Abinaya, P. and Poornimasre, J., "Non-intrusive bit swapping pattern generator for bist testing of luts", in Information Communication and Embedded Systems (ICICES), International Conference on, IEEE., (2014), 1-4.
14.   Praveen, J. and Shanmukhaswamy, M.N., "Power reduction technique in lfsr using modified control logic for vlsi circuit",  International Journal of Computer Applications, No. 4, (2013), 21-24.
15.   Krishna, K.M. and Sailaja, M., "Low power memory built in self test address generator using clock controlled linear feedback shift registers", Journal of Electronic Testing,  Vol. 30, No. 1, (2014), 77-85.
16.   Kaur, K. and Noor, A., "Strategies & methodologies for low power vlsi designs: A review", International J. Advances in Engineering & Technology,  Vol. 1, (2011), 159-165.
17.   Li, C., Zeng, X., Helleseth, T., Li, C. and Hu, L., "The properties of a class of linear fsrs and their applications to the construction of nonlinear fsrs", IEEE Transactions on Information Theory,  Vol. 60, No. 5, (2014), 3052-3061.
18.   Marufuzzaman, M., Rosly, H.N.B., Reaz, M.B.I., Rahman, L.F. and Hussain, H., "Design of low power linear feedback shift", Journal of Theoretical & Applied Information Technology,  Vol. 61, No. 2, (2014), 326-333.
19.   Sowmiya, G., Premalatha, P., Rajaram, A., Saravanan, S. and Sai, R.V., "Design and analysis of scan power reduction based on linear feedback shift register reseeding", in Information & Communication Technologies (ICT), IEEE Conference on, IEEE., (2013), 638-641.
20.   Ahmad, A. and Al-Maashri, A., "Investigating some special sequence lengths generated in an external exclusive-nor type LFSR", Computers & Electrical Engineering,  Vol. 34, No. 4, (2008), 270-280.
21.   Saraswathi, T., Ragini, K. and Ch, G.R., "A review on power optimization of linear feedback shift register (lfsr) for low power built in self test (BIST)", in Electronics Computer Technology (ICECT), 3rd International Conference on, Vol. 6, (2011), 172-176.
22.   Kavitha, A., Seetharaman, G., Prabakar, T. and Shrinithi, S., "Design of low power tpg using lp-lfsr", in Intelligent Systems, Modelling and Simulation (ISMS), Third International Conference on, IEEE., (2012), 334-338.
23.   Muthammal, R. and Joseph, K., "Low power efficient built in self test", in Microwaves, Communications, Antennas and Electronics Systems (COMCAS), International Conference on, IEEE., (2011), 1-5.
24.   Zadeh, A.A. and Heys, H.M., "Simple power analysis applied to nonlinear feedback shift registers", IET Information Security,  Vol. 8, No. 3, (2014), 188-198.
25.   Rebaud, B., Belleville, M., Bernard, C., Robert, M., Maurine, P. and Azemard, N., "A comparative study of variability impact on static flip-flop timing characteristics", in Integrated Circuit Design and Technology and Tutorial,. ICICDT. IEEE International Conference on,.(2008), 167-170.
26.   Sheela, T., Muthumanickam, T. and Nagappan, A., "A lfsr based binary numeral system using cmos vlsi", International Journal of VLSI and Embedded Systems-IJVES ISSN,  No. 2249-6556.
27.   Rani, M.J. and Malarkkan, S., "Design and analysis of a linear feedback shift register with reduced leakage power", International Journal of Computer Applications,  Vol. 56, No. 14, (2012).
28.   Sahu, V. and Kumar, M.P., "Power reduction and speed augmentation in lfsr for improved sequence generation using transistor stacking method", International Journal of Computer Trends and Technology (IJCTT),  Vol. 4, No. 4, (2013).