, Royal Institute of Technology & Science
, GITAM Institute of Technology, GITAM University
Eletronic and Communication Engineering, GITAM Institute of Technology, GITAM University
The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed memory test algorithm, the self-testing as well as self-repair mechanisms are incorporated. This scheme repairs the detected faults and is easily integrated with SoC design. Here, an attempt has been made to implement the memory built-in-self-repair (MBISR) architecture to test and repair the faults from the embedded memories. It is little, and it supports at-fast test without timing penalty during its operation. The proposed method is a better alternative in speed and low area overhead. Thus, it plays a significant role in yield improvement.