Abstract




 
   

IJE TRANSACTIONS C: Aspects Vol. 31, No. 9 (September 2018) 1546-1552    Article in Press

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  LOW DROPOUT BASED NOISE MINIMIZATION OF ACTIVE MODE POWER GATED CIRCUIT
 
D. Nath and S. N. Pradhan
 
( Received: March 10, 2016 – Accepted in Revised Form: April 01, 2018 )
 
 

Abstract    The presence of package inductance induces large voltage fluctuation (bounce noise) on the power rail during power down to power up transition in the power gating circuit that may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode. Noise for the architecture has also been analyzed. The effect of various noise minimization approaches for reducing power supply noise have been evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage Regulator has been proposed in this paper. The amount of charge in the internal nodes that passes through the sleep transistor during the wake-up transition has been controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed with a target of reducing bounce noise by minimizing voltage fluctuations on the power rail. Low noise active mode power gating architectures have been designed in Synopsys Custom Designer tool at iPDK 90nm technology. Saving of noise at the power supply rail has been observed up to 99%.

 

Keywords    Architecture, Power-gating, Data-retention, Leakage Noise, Low-dropout Voltage

 

چکیده   

حضور بسته القایی باعث ایجاد نوسان ولتاژ بالا (بانس نویز) در طی انتقال توان بالا به پایین بر روی ریل قدرت در مدار گیت قدرت می‌شود که ممکن است تغییرات ناخواسته را در مدارهای مجاور ایجاد کند. در این کار یک طراحی گیت قدرت برای کاهش توان در حالت فعال توسعه داده شده است. نویز نیز برای این طراحی تحلیل شده است. تأثیر روش‌های مختلف کاهش نویز برای کاهش نویز منبع تغذیه در طراحی گیت قدرت ارزیابی شده است. در این مقاله، یک مفهوم جدید از روش کمینه‌سازی نویز با استفاده از رگولاتور ولتاژ خروجی پایین پیشنهاد شده است. مقدار شارژ در گره‌های داخلی که از طریق ترانزیستور خواب در طول گذر از بیداری عبور می‌کند، توسط تکنیک‌های کمینه‌سازی نویز پیشنهاد شده کنترل شده است. رگولاتور ولتاژ پایین خروجی با هدف کاهش نویز گشتاور از طریق به حداقل رساندن نوسانات ولتاژ بر روی ریل قدرت طراحی شده است. طراحی‌های گیت قدرت در حالت فعال و نویز کم توسط ابزار Synopsys Custom Designer در تکنولوژی 90 nm iPDK طراحی شده‌اند. صرفه‌جویی در نویز در ریل منبع تغذیه تا 99٪ مشاهده شده است.

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