TY - JOUR ID - 72100 TI - High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop JO - International Journal of Engineering JA - IJE LA - en SN - 1025-2495 AU - Sharma, Yateesh AU - Singh, N.P. AU - Juneja, Kapil AD - Electronics & Communications Engineering, National Institute of Technology Kurukhshetra Y1 - 2013 PY - 2013 VL - 26 IS - 3 SP - 315 EP - 322 KW - low power KW - Level Conversion KW - Flip KW - Flops KW - multi KW - VDD Systems DO - N2 - Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this paper, an improved version of clocked pseudo-NMOS LCFF called Clock Branch Sharing pseudo-NMOS LCFF has been proposed, which combines the Conditional Discharge technique, pseudo-NMOS technique and Clock Branch Sharing technique. Based on Simulation results, the proposed flip-flop exhibits up to 32.5% delay reduction and saves power up to 8.1% as compared to clocked pseudo-NMOS LCFF. UR - https://www.ije.ir/article_72100.html L1 - https://www.ije.ir/article_72100_f68b17db1e1d2a08ebfdb1cec56a1d64.pdf ER -